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Verification Methodology Manual for SystemVerilog, by Janick Bergeron, Eduard Cerny, Alan Hunter, Andy Nightingale
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Offers users�the first resource guide that combines�both the�methodology and basics of SystemVerilog
Addresses how all these pieces fit together and how they should be used to verify complex chips rapidly and thoroughly.
Unique in its broad coverage of SystemVerilog, advanced functional verification, and the combination of the two.
- Sales Rank: #551665 in Books
- Published on: 2005-09-28
- Original language: English
- Number of items: 1
- Dimensions: 9.21" h x 1.13" w x 6.14" l, 1.86 pounds
- Binding: Hardcover
- 503 pages
About the Author
Janick Bergeron is a Scientist at Synopsys, Inc. He is the author of the best-selling book Writing Testbenches: Functional Verification of HDL Models and the moderator of the Verification Guild. Prior to joining Synopsys, Janick worked on verification methodology at Qualis Design Corporation and Bell-Northern Research. He holds a Masters degree in Electrical Engineering from the University of Waterloo, a Bachelor of Science degree in Engineering from the Universit� du Qu�bec, and an MBA degree granted through the University of Oregon.
Eduard Cerny is a Principal Engineer, R&D, in the Verification Group at Synopsys, Inc. He joined Synopsys in 2001 after 25 years in academia, as Professor of Computer Science at the Universit� de Montr�al. Eduard has a B.Sc. in Electrical Engineering from Loyola College in Montreal, Canada, and a M.Eng. and Ph.D. in Electrical Engineering from McGill University in Montreal, Canada. His interests have been in design, verification and test of hardware, and he is author of many articles in these areas.
Alan Hunter, BEng(Hons), MSc, is the Design Verification Methodology Programme manager at ARM Ltd. and is leading the design verification methodology work for ARM worldwide. This work covers all areas from CPU design verification through systems and system component design verification. His main areas of interest include optimizing design verification efficiency and quality, formal methods, and determinism in the design verification flow. Prior to joining ARM, Alan worked for a small formal verification company specializing in property and equivalence checking.
Andy Nightingale, BEng(Hons), MBCS CITP, is a consultant engineer at ARM Ltd and has led the SoC Verification group in ARM’s Cambridge and Sheffield design centers for the past four years. The group covers ARM PrimeXSys platforms and PrimeCell development, including advanced AXI- and AHB-based system backplane components such as bus interconnects and high-performance memory controllers. Prior to working at ARM, Andy worked as a real-time embedded systems engineer for a successful scientific instrument company, primarily serving the semiconductor industry.
Most helpful customer reviews
5 of 5 people found the following review helpful.
Good Reference
By Kris M
I consider this book to be a good VMM Reference.
Please don't mistake this to be a complete SystemVerilog Bible. This is Verification Methodology Manual (VMM), and after reading this book, it's not a bad idea to think if this methodology is the right one for your project.
This book outlines several "rules", "recommendations", "suggestions" and "alternatives" in using VMM for your project. I found these to be useful to a certain extent. Although the examples weren't quite informative. For starters I would also suggest reading general book on object oriented programming along with this book.
************* BUYING THIS BOOK? READ THIS: ***************
Before you buy this book, check if you/your office has Synopsys VCS installed (Along with Documentation). If you happen to have complete VCS installed, you would get this book (pdf version) for FREE along with the VCS documentation. I came to know about this after buying this book. Any ways, it is good to have a hard copy.
Also, I found it useful to have other SystemVerilog books along with this one. It makes life easy to understand a (new) language and (new) methodology.
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1 of 1 people found the following review helpful.
VMM is difficult
By Timothy H. Pylant
The book starts off fairly well through the first three chapters. Then all of a sudden it makes a huge leap and it becomes very difficult to follow. There are a lot of very advanced topics that require a lot of object oriented programming experience to understand. On my second reading I saw that even Janick says that he does not expect you to understand VMM on the first reading.
A class based methodology is a complex topic and the VMM book does not do much to make it any easier. If you are a C++ (or something similar) guru, then you might enjoy this book. Otherwise, save your money and download the white papers from the web.
0 of 0 people found the following review helpful.
Great book to learn about VMM.
By Kevork V. Dikramanjian
I got this book at work to learn about VMM and the use of it.
It covers high level concepts and recommendations on developing a successful verification environment. It does not teach you the syntax or the basics of System Verilog. Beside teaching you these high level concepts, it covers in detail the use of the VMM base classes offered with Synopsys' VCS tools.
The book has code example in each topic covered which will make it easier to understand.
The topics covered include, but not limited to, Verification planning, assertions, testbench infrastructure, stimulus/response and coverage.
If you are using VMM in your development, then this book is definitely the manual that goes with it.
A must have for a successful verification engineer working with VMM. (6 out of 5 stars)
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